Successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used because of a variety of advantages including a medium conversion accuracy (8-16 bits), a medium conversion rate (up to 5 Msps), a low power consumption, a low cost, compatibility with modern CMOS processes and easy scaling down.
FIG. 1 is a schematic view of a conventional SAR ADC, comprising a sample-and-hold circuit, an N-bit digital-to-analog converter (DAC), a comparator 103 and an SAR control logic circuit 102. In general, the sample-and-hold circuit and the N-bit DAC is both provided by a capacitor array 101. As an important component relating to conversion accuracy and rate, the DAC plays a key role in halving a reference voltage (Vref).
The SAR ADC performs binary searches to determine the closest digital value that fits an analog input signal.
The analog input signal, i.e., an input voltage Vin, is compared to known reference voltages Vrefn and Vrefp for multiple times under a control of the SAR control logic circuit 102 so that the converted digital numbers successively approximate the numerical value corresponding to the input analog quantity.
In the sampling phase, the analog input signal is sampled onto the capacitor array 101 of the DAC.
After the conversion begins, under the control of a clock input, the SAR control logic circuit 102 controls the N-bit DAC to output a ½Vref analog signal, followed by comparing the sampled signal with ½Vref to determine the most significant bit (MSB). A second comparison is then performed, in which the N-bit DAC outputs a ¾Vref or ¼Vref analog signal based on the MSB value, and the sampled signal is then compared with ¾Vref or ¼Vref to determine the second MSB. This process is repeated, with the comparator 103 successively comparing the input signal, until the least significant bit (LSB) is determined, thereby completing the algorithm.
The sample-and-hold circuit and the N-bit DAC are usually both provided by the capacitor array 101. FIG. 2 shows a conventional 12-bit SAR ADC adopting a single-stage capacitor array architecture known to include 12 binary-weighted capacitors and one terminating capacitor C113. The binary-weighted capacitors' capacitance is successively doubled, from that of the LSB capacitor C101 defined as one unit of capacitance C to that of the MSB capacitor C112 equating to 211 C. The terminating capacitor C113 also has a capacitance of 1 C. Top plates of the binary-weighted capacitors and of the terminating capacitor C113 are connected together and provide an output Vout. In addition, bottom plates of the binary-weighted capacitors and of the terminating capacitor C113 are coupled to respective one-pole-three-throw (SP3T) switches. Under the control of a control signal, each of the SP3T switches is coupled at the other end to one of the input voltage Vin, the positive reference voltage Vrefp and the negative reference voltage Vrefn. In scenarios where the differential reference voltage signals Vrefp and Vrefn are not used, each of the SP3T switches may alternatively be, under the control of a control signal, coupled at the other end to one of the input voltage Vin, a reference voltage and the ground. The output Vout is coupled to a common-mode level Vcm via a switch.
Most existing 12-bit SAR ADC capacitor arrays adopt a two-stage architecture having two capacitor arrays which are connected together by a coupling capacitor and have the same binary-weighted bits in order to minimize the energy consumption of capacitors and switches. Such as a conventional 12-bit SAR ADC two-stage capacitor array, as shown in FIG. 3, has a first capacitor sub-array and a second capacitor sub-array connected thereto by a coupling capacitor C214. The first capacitor sub-array contains binary-weighted capacitors C201-C206 and a terminating capacitor C213, and the second capacitor sub-array contains binary-weighted capacitors C207-C212. Capacitances of the aforesaid respective capacitors are also given in FIG. 3. In order to comply with the binary weighting scheme, the coupling capacitor is selected as a fractional capacitor having a capacitance of 64/63 C so that compared to a change that a signal will experience when it is input at the bottom plate of the binary-weighted capacitor C206 and output from the output Vout, it will change by twice as much when it is input at the bottom plate of the binary-weighted capacitor C207 and output from the output Vout.
There are also conventional 12-bit SAR ADCs using three-stage capacitor arrays.
An analog-to-digital (A/D) conversion performed by a conventional SAR ADC on an analog input signal consists of repeated cycles of sampling and SAR A/D conversion until the A/D conversion is completed. FIG. 4 is a diagram illustrating the timings of an A/D conversion process of a conventional 12-bit SAR ADC, the timings including operating timing, corresponding clock and sampling signal timing.
When the sampling signal is at a high level, the analog input signal is sampled, and the sampling lasts for one cycle of the clock signal, i.e., the clock cycle indicated at 1 in FIG. 4.
An idle cycle follows, in which nothing is done, i.e., the clock cycle indicated at 2 in the figure.
Subsequently, 12 successively A/D conversions are carried out, indicated respectively at Bit1, Bit2, . . . , Bit12 in FIG. 4. Wherein, Bit1 denotes the conversion for deriving a value for the MSB (the twelfth bit) in a target 12-bit digital output signal; Bit2, that for deriving a value for the eleventh bit therein; . . . ; and Bit12, that for deriving a value for the lowest first bit therein, and hence the successive A/D conversions of the sampling signal are completed. After that, another sample-and-convert cycle is commenced. As can be seen from the figure, each of those successive A/D conversions for obtaining the value of a corresponding bit lasts for one clock cycle. That is, they last for a total period of 12 clock cycles, i.e., those respectively indicated at 3, 4, . . . , 14 in FIG. 4.
Therefore, each sample-and-convert cycle in the conventional SAR A/D conversion process covers 14 clock cycles. However, in practice, as the analog input signal is usually a continuous signal, any two successive sampled analog signals typically do not differ much from each other. As a result, the two digital output signals converted from those two analog signals tend to assume the same values at several highest bits and exhibit differences at the remaining low bits. For this reason, the conventional SAR A/D conversion solution that treats each sampled signal with the complete process spanning 14 clock cycles is considered to have a low clock utilization and an unnecessary power consumption.